// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
/*
 * Copyright (C) 2022 liujuan1@allwinnertech.com
 */

#ifndef _DT_BINDINGS_CLK_SUN60IW1_H_
#define _DT_BINDINGS_CLK_SUN60IW1_H_

#define CLK_PLL_REF		0
#define CLK_PLL_DDR		1
#define CLK_PLL_PERI0		2
#define CLK_PLL_PERI0_2X	3
#define CLK_PERI0_DIV3		4
#define CLK_PLL_PERI0_800M	5
#define CLK_PLL_PERI0_480M	6
#define CLK_PLL_PERI0_600M	7
#define CLK_PLL_PERI0_400M	8
#define CLK_PLL_PERI0_300M	9
#define CLK_PLL_PERI0_200M	10
#define CLK_PLL_PERI0_160M	11
#define CLK_PLL_PERI0_150M	12
#define CLK_PLL_PERI1		13
#define CLK_PLL_PERI1_2X	14
#define CLK_PLL_PERI1_800M	15
#define CLK_PLL_PERI1_480M	16
#define CLK_PLL_PERI1_600M	17
#define CLK_PLL_PERI1_400M	18
#define CLK_PLL_PERI1_300M	19
#define CLK_PLL_PERI1_200M	20
#define CLK_PLL_PERI1_160M	21
#define CLK_PLL_PERI1_150M	22
#define CLK_PLL_GPU0		23
#define CLK_PLL_VIDEO0_4X	24
#define CLK_PLL_VIDEO0_3X	25
#define CLK_PLL_VIDEO1_4X	26
#define CLK_PLL_VIDEO1_3X	27
#define CLK_PLL_VIDEO2_4X	28
#define CLK_PLL_VIDEO2_3X	29
#define CLK_PLL_VIDEO3_4X	30
#define CLK_PLL_VIDEO3_3X	31
#define CLK_PLL_VE0		32
#define CLK_PLL_VE1		33
#define CLK_PLL_AUDIO0_4X	34
#define CLK_PLL_NPU		35
#define CLK_PLL_DE_4X		36
#define CLK_PLL_DE_3X		37
#define CLK_PLL_CCI		38
#define CLK_AHB			39
#define CLK_APB0		40
#define CLK_APB1		41
#define CLK_APB_UART		42
#define CLK_TRACE		43
#define CLK_CCI			44
#define CLK_GIC0		45
#define CLK_GIC1		46
#define CLK_NSI			47
#define CLK_MBUS		48
#define CLK_MSI_LITE0		49
#define CLK_MSI_LITE1		50
#define CLK_VE_ENC1_MBUS	51
#define CLK_VE_DEC_MBUS		52
#define CLK_GMAC1_MBUS		53
#define CLK_GMAC0_MBUS		54
#define CLK_ISP_MBUS		55
#define CLK_CSI_MBUS		56
#define CLK_NAND_MBUS		57
#define CLK_DMA1_MBUS		58
#define CLK_CE_MBUS		59
#define CLK_VE_ENC0_MBUS	60
#define CLK_DMA0_MBUS		61
#define CLK_DMA0_BUS		62
#define CLK_DMA1_BUS		63
#define CLK_SPINLOCK_BUS	64
#define CLK_MSGBOX0_CLK		65
#define CLK_MSGBOX1_CLK		66
#define CLK_MSGBOX2_CLK		67
#define CLK_PWM0_CLK		68
#define CLK_PWM1_CLK		69
#define CLK_DBGSYS_CLK		70
#define CLK_DBGPAD_CLK		71
#define CLK_TIMER0_CLK0		72
#define CLK_TIMER0_CLK1		73
#define CLK_TIMER0_CLK2		74
#define CLK_TIMER0_CLK3		75
#define CLK_TIMER0_CLK4		76
#define CLK_TIMER0_CLK5		77
#define CLK_TIMER0_CLK6		78
#define CLK_TIMER0_CLK7		79
#define CLK_TIMER0_CLK8		80
#define CLK_TIMER0_CLK9		81
#define CLK_TIMER0		82
#define CLK_TIMER1_CLK0		83
#define CLK_TIMER1_CLK1		84
#define CLK_TIMER1_CLK2		85
#define CLK_TIMER1_CLK3		86
#define CLK_TIMER1_CLK4		87
#define CLK_TIMER1_CLK5		88
#define CLK_TIMER1		89
#define CLK_DE0			90
#define CLK_DE0_BUS		91
#define CLK_DE1			92
#define CLK_DE1_BUS		93
#define CLK_DI			94
#define CLK_DI_BUS		95
#define CLK_G2D			96
#define CLK_G2D_BUS		97
#define CLK_VE_ENC0		98
#define CLK_VE_ENC1		99
#define CLK_VE_DEC		100
#define CLK_VE_ENC1_BUS		101
#define CLK_VE_ENC0_BUS		102
#define CLK_CE			103
#define CLK_CE_SYS		104
#define CLK_CE_BUS		105
#define CLK_NPU			106
#define CLK_NPU_BUS		107
#define CLK_AIPU		108
#define CLK_AIPU_BUS		109
#define CLK_GPU0		110
#define CLK_GPU0_BUS		111
#define CLK_DSP			112
#define CLK_DRAM0		113
#define CLK_DRAM0_BUS		114
#define CLK_NAND0_CLK0		115
#define CLK_NAND0_CLK1		116
#define CLK_NAND0_BUS		117
#define CLK_SMHC0		118
#define CLK_SMHC0_24M		119
#define CLK_SMHC0_BUS		120
#define CLK_SMHC1		121
#define CLK_SMHC1_BUS		122
#define CLK_SMHC2		123
#define CLK_SMHC2_24M		124
#define CLK_SMHC2_BUS		125
#define CLK_SMHC3		126
#define CLK_SMHC3_24M		127
#define CLK_SMHC3_BUS		128
#define CLK_UFS_AXI		129
#define CLK_UFS			130
#define CLK_UART0		131
#define CLK_UART1		132
#define CLK_UART2		133
#define CLK_UART3		134
#define CLK_UART4		135
#define CLK_UART5		136
#define CLK_UART6		137
#define CLK_UART7		138
#define CLK_UART8		139
#define CLK_TWI0		140
#define CLK_TWI1		141
#define CLK_TWI2		142
#define CLK_TWI3		143
#define CLK_TWI4		144
#define CLK_TWI5		145
#define CLK_TWI6		146
#define CLK_TWI7		147
#define CLK_TWI8		148
#define CLK_SPI0		149
#define CLK_SPI0_BUS		150
#define CLK_SPI1		151
#define CLK_SPI1_BUS		152
#define CLK_SPI2		153
#define CLK_SPI2_BUS		154
#define CLK_SPIF		155
#define CLK_SPIF_BUS		156
#define CLK_SPIF3		157
#define CLK_SPIF3_BUS		158
#define CLK_SPIF4		159
#define CLK_SPIF4_BUS		160
#define CLK_SPIF5		161
#define CLK_SPIF5_BUS		162
#define CLK_SPIF6		163
#define CLK_SPIF6_BUS		164
#define CLK_GPADC0_24M		165
#define CLK_GPADC0		166
#define CLK_GPADC1_24M		167
#define CLK_GPADC1		168
#define CLK_THS0		169
#define CLK_IRRX		170
#define CLK_IRRX_BUS		171
#define CLK_IRTX		172
#define CLK_IRTX_BUS		173
#define CLK_LRADC		174
#define CLK_LBC			175
#define CLK_LBC_BUS		176
#define CLK_I2SPCM1		177
#define CLK_I2SPCM1_BUS		178
#define CLK_I2SPCM2		179
#define CLK_I2SPCM2_ASRC	180
#define CLK_I2SPCM2_BUS		181
#define CLK_I2SPCM3		182
#define CLK_I2SPCM4		183
#define CLK_I2SPCM4_BUS		184
#define CLK_I2SPCM5		185
#define CLK_I2SPCM5_BUS		186
#define CLK_SPDIF_TX		187
#define CLK_SPDIF_RX		188
#define CLK_SPDIF		189
#define CLK_USB2_HOST0		190
#define CLK_USB2_OTG0		191
#define CLK_USB2_EHCI0		192
#define CLK_USB2_OHCI0		193
#define CLK_USB2_HOST1		194
#define CLK_USB2_OHCI1		195
#define CLK_USB2_HOST2		196
#define CLK_USB2_EHCI2		197
#define CLK_USB2_OHCI2		198
#define CLK_USB2_REF		199
#define CLK_USB3_USB2_REF	200
#define CLK_USB3_SUSPEND	201
#define CLK_USB3_MF		202
#define CLK_PCIE0_AUX		203
#define CLK_GMAC_PTP		204
#define CLK_GMAC0_PHY		205
#define CLK_GMAC0		206
#define CLK_GMAC1_PHY		207
#define CLK_GMAC1		208
#define CLK_VO0_TCONLCD0	209
#define CLK_VO0_TCONLCD0_BUS	210
#define CLK_VO0_TCONLCD1	211
#define CLK_VO0_TCONLCD1_BUS	212
#define CLK_VO0_TCONLCD2	213
#define CLK_VO0_TCONLCD2_BUS	214
#define CLK_VO0_TCONLCD3	215
#define CLK_VO0_TCONLCD3_BUS	216
#define CLK_DSI0		217
#define CLK_DSI0_BUS		218
#define CLK_DSI1		219
#define CLK_DSI1_BUS		220
#define CLK_COMBPHY0		221
#define CLK_COMBPHY1		222
#define CLK_TCONTV0		223
#define CLK_TCONTV0_BUS		224
#define CLK_TCONTV1		225
#define CLK_TCONTV2		226
#define CLK_EDP_CLK0		227
#define CLK_EDP_CLK1		228
#define CLK_EDP_BUS		229
#define CLK_HDMI_REF		230
#define CLK_HDMI_PRE		231
#define CLK_HDMI_HDCP		232
#define CLK_HDMI		233
#define CLK_DPSS_TOP0		234
#define CLK_DPSS_TOP1		235
#define CLK_LEDC		236
#define CLK_LEDC_BUS		237
#define CLK_CSI_MASTER0		238
#define CLK_CSI_MASTER1		239
#define CLK_CSI_MASTER2		240
#define CLK_CSI_MASTER3		241
#define CLK_CSI			242
#define CLK_BUS_CSI		243
#define CLK_ISP			244

#endif /* _DT_BINDINGS_CLK_SUN60IW1_H_ */
